Huawei Semiconductor Chief Warns: NVIDIA Chip Scale Expansion Approaching Physical Limits, Crossing the Tipping Point Will Trigger a 'Snowball Effect'

August 4th. In a recent public interview, Liao Heng, Chief Scientist of Huawei's Semiconductor Division and one of the key architects of the Ascend AI chip, issued a warning. He mentioned that Western chip giants, with NVIDIA as a representative, are approaching a physical limit in the pursuit of more powerful processors. He stated, "There is inevitably a ceiling to scale by continuously increasing computing cores and more HBM. The industry is still advancing, but once this physical limit is crossed, an avalanche will occur."

Liao Heng metaphorically compared the entire AI value chain to an "18-story tower," in response to NVIDIA CEO Jensen Huang's "layer cake" framework. He emphasized that China needs to establish collaborative capabilities at every layer, especially emphasizing the need for close cooperation between chip manufacturers and AI model developers. Liao Heng also revealed that Huawei is about to release its first smartphone chip designed based on the Tau Scaling Law framework, achieved through LogicFolding technology. After institutions such as SemiAnalysis and TechInsights dissect and analyze it, "the world will clearly understand later this year how this alternative path helps narrow the gap."

The Tau Scaling Law is an innovative design concept proposed by Huawei, focusing on increasing the transmission speed between various components of a computer system as the inherent advantages of chip miniaturization diminish.

Liao Heng also highly praised DeepSeek founder Liang Wenfeng, stating that the key to training top models with extremely low computing power by 2025 lies in the innovative design of the model architecture. He likened Chinese AI innovation to maximizing space in a small apartment, while Western counterparts live in more spacious villas. Liao Heng stated that Huawei itself is developing AI chips that can better support efficient architectures through a mechanism of chip-model co-design. "We must invest more effort in design to trade higher complexity for less computing resource consumption."