SemiAnalysis In-Depth Analysis of Yangtze Memory Technologies: $50 Billion Revenue, IPO During a Super Cycle

Original Title: China‘s CXMT Is Set to Challenge DRAM Incumbents
Original Source: SemiAnalysis
Original Translation: DeepTech TechFlow

DeepTech Summary: YMTC is about to go public on the Science and Technology Innovation Board, poised to become the largest semiconductor IPO in Chinese history. This company, founded in 2016, started by acquiring the patents and talent of the bankrupt German DRAM manufacturer Innotron Memory, and with the capital infusion from the Hefei government that tolerated nearly a decade of losses, turned profitable in 2025, with first-quarter revenue in 2026 reaching $7.3 billion. SemiAnalysis's in-depth report breaks down YMTC's technological path, financial data, HBM dilemma, and IPO structure, making it essential reading to understand China's position in the memory chip industry.

The SemiAnalysis team was among the first to describe in their newsletter at the end of 2024 the significant demand for memory from AI inference and autonomous agent workflows. They have since released multiple in-depth memory reports and continued to track YMTC and China's computing power ecosystem. As YMTC is set to go public in the coming months, a dedicated in-depth study becomes necessary. YMTC is likely to become the largest semiconductor IPO in China and a milestone for this top Chinese memory manufacturer. From here on, the competition between YMTC and Samsung, SK Hynix, and Micron will only intensify.

Returnee of Silicon Valley

YMTC's founder, Zhu Yiming, graduated from Tsinghua University with a degree in Physics in 1994, then went to study Electrical Engineering at the State University of New York at Stony Brook. He worked in Silicon Valley for many years and became a project leader at MoSys (Monolithic System Technology) around 2001. In 2005, Zhu Yiming returned to China with a group of SRAM patents and $100,000 in seed funding, founding GigaDevice, which later became one of the world's top NOR Flash suppliers. However, the global NOR Flash market is much smaller than DRAM or NAND Flash. Zhu Yiming's ambition was greater, so he chose the DRAM track.

DRAM is not a game for fabless companies. DRAM consumes capital, has strict patent barriers, and is highly reliant on manufacturing capabilities. By 2016, the entire industry had only three survivors: Samsung, SK Hynix, and Micron. The patent and capital moat built up over forty years made it impossible for new players to break through. Zhu Yiming's SRAM patents and GigaDevice's NOR Flash business could not provide DRAM memory unit designs, nor could they offer DRAM processes, let alone bypass the giants' patent blockade. Therefore, when Zhu Yiming and the Hefei municipal government launched the DRAM project "Project 506" in 2016 (later known as YMTC), the core technology had to be obtained from external sources.

The source is a now-defunct German company.

DRAM Roots: The Legacy of Qimonda

The deceased company in question is Qimonda. Qimonda filed for bankruptcy in January 2009 due to the global financial crisis and the subsequent memory price collapse, but at the time, it was a leading DRAM manufacturer in Europe. As a subsidiary of Infineon, itself a spinoff from Siemens, Qimonda offered a rare alternative: a deep DRAM patent portfolio and a set of memory cell architectures, both outside the Samsung-Hynix-Micron triad.

In June 2015, Canadian patent licensing company WiLAN's subsidiary, Polaris Innovations, acquired around 7,000 Qimonda patents and applications from Infineon for approximately €30 million. In December 2019, Polaris signed an agreement with ChangXin Memory Technologies, granting them access to a large number of DRAM patents. Senior executives at ChangXin publicly stated that they obtained around 2.8 TB of Qimonda technical documents, which became the foundation of ChangXin's DRAM business.

One key technology inherited and developed by ChangXin from Qimonda is the 46nm-level Buried Wordline (BWL) memory cell, which they have pushed to the 10nm level. BWL is a core architectural innovation. While traditional approaches wire the gate of the access transistor along the wafer surface, BWL embeds the gate below the wordline in a trench. This provides three benefits: shrinking the memory cell to a 6F² layout (compared to the traditional 8F²), elongating the channel length under the premise of not occupying surface area to suppress short-channel leakage (which affects data retention), and reducing gate-wordline parasitic capacitance. The buried wordline, along with stacked capacitors, is the architecture used by the three major memory giants today. Qimonda, which adhered to the trench scheme back in the day, happened to retain the stacked/BWL technological reserves—and ChangXin stumbled upon it.

Talent: From Frozen Blueprints to Living R&D Capability

Apart from patents, ChangXin's more enduring asset inherited from Qimonda's collapse is its engineers. Qimonda had a research and development center in Xi'an with 400-500 engineers, one of its largest R&D hubs outside of Germany. Following Qimonda's bankruptcy, while the entire Xi'an R&D center was acquired by Tsinghua Unigroup, the wider dispersion of talent also benefited ChangXin.

ChangXin also successfully attracted senior engineer Karl-Heinz Kuesters from Qimonda's German headquarters. Kuesters had served as Vice President of Technology and Predevelopment at Siemens, Infineon, and Qimonda for 24 years. The pre-development line he led was the stacked capacitor approach—the same architecture ChangXin actually adopted. He joined ChangXin as a technical advisor, with EE Times calling Kuesters the "ace" of ChangXin. What Kuesters brought was implicit knowledge that neither patents nor the 2.8 TB documents could capture: two decades of leading DRAM development, enabling him to guide ChangXin engineers on which of Qimonda's designs to retain, which to discard, and how to transition lab-proven memory cells into mass production. This kind of integration and yield judgment is not found in any patent literature.

The same pattern applies to the United States as well. ChangXin's Vice President responsible for future technology assessment, Ping Er-xuan (the public presenter of the "46 nm to 10 nm level" roadmap), did not come from Qimonda, but from a U.S. career at Micron, SanDisk, and Applied Materials, with deep expertise in memory and material technology.

ChangXin has also recruited heavily from South Korea and Taiwan. South Korean prosecutors have previously indicted former Samsung employees for technology leakage, with reports indicating that dozens of Korean engineers have worked at ChangXin. A similar situation exists in Taiwan, where ChangXin offers generous salaries to continuously poach top equipment and process engineers.

This is the key to understanding ChangXin's trajectory. Qimonda's patents have always been limited, expiring assets. What allowed ChangXin to advance from G4 to G5 and then to HBM is the consolidated talent pool—locally cultivated talent, Chinese engineers who returned to their home country after working for foreign companies, and a small number of foreign experts—rather than documents. Heritage was just the starting point; talent transformed foreign heritage into a self-developed engine. However, it took nearly a decade for this engine to become profitable. The question is, who has the patience to continue providing support?

SOE Venture Capital's Patience

ChangXin's success can hardly be attributed to anything other than strong support from both local and central Chinese governments. The Hefei city government is a classic example. Hefei is a key hub for scientific and technological innovation in China and has, over the past twenty years, nurtured a group of successful enterprises through a "patient state-owned enterprise (SOE) venture capital" model: BOE Technology Group (a global leader in display panels), NIO (a leading electric vehicle manufacturer), and now it's ChangXin Storage's turn.

The Hefei city government has done two key things for ChangXin.

First, they helped ChangXin build a local supply chain around the factory. Hefei's strategy is to hold a large stake in the core "anchor" enterprise, then attract the rest of the industrial chain. This strategy has been applied in the display panel sector with BOE and in the electric vehicle sector with NIO, and since 2016, ChangXin has followed the same playbook. Around ChangXin's factory in the Hefei Airport Economic Zone, the government has created a dense local industrial cluster. Packaging and testing plant Pacton and Siliconpire are located next to ChangXin's plant, with Siliconpire generating over 99% of its revenue from ChangXin. Light Steel operates an on-site bulk gas manufacturing plant that supplies most of ChangXin's needs, while Zhiwei Semiconductor under Schott Solar provides wafer recycling capacity in the Hefei New Station High-tech Zone. SOE Venture Capital also directly holds shares in upstream chip molding equipment manufacturer Welly Power.

Second, the Hefei SOEs are willing to endure losses for a long time. Unlike private equity funds that need to deliver returns to their limited partners regularly, Hefei's SOE venture capital is ultimately supported by municipal and development zone entities with no exit clock. They have continued to provide funding to a company that didn't turn an annual profit until 2025, accumulating losses of approximately 36.65 billion RMB over nearly a decade. Launched in 2016, the "506 Project" received around 80% of its initial funds (14.4 billion/18 billion RMB) from Hefei SOEs. Although Hefei's state-owned assets were diluted in subsequent rounds of financing, they never reduced their holdings or exited. By the time of the IPO, the largest shareholder, Hefei Qinghui Power Hold, held a 21.67% stake, with SOE venture capital holding over 30% collectively. The willingness to treat the wafer plant as a ten-year bet rather than a fund cycle return—the catalyst on which both technology and talent rely.

From Legacy to Autonomy

The first decade of Changxin became clear as three threads intertwined. Qimonda provided the foundation: an authorized patent pool and storage unit architecture from outside the big three giants. Talent provided the driving force: key figures like Kuesters and Ping, along with returnees from American giants and controversially poached talents from Korea, who turned the frozen blueprint into a sustainable process. Then the Hefei government provided something the former two needed but couldn't generate on their own: capital, patience, and a localized supply chain. All three were indispensable.

Next comes the discussion of Changxin's financial, technical, and equipment ecosystem.

Next Step After a Decade: IPO in a Super Cycle

While Changxin's story of the past decade is impressive, it may just be the early chapter of a longer narrative. The company is preparing for one of China's largest semiconductor IPOs in recent years, and possibly the most anticipated semiconductor listing globally this year. In December 2025, the Shanghai Stock Exchange officially accepted Changxin's application for the Sci-Tech Innovation Board. Prior to this, there had been market rumors in 2024 and 2025 about the company preparing for an IPO. The latest development is that Changxin submitted its registration application to the CSRC on May 27 and is currently in the final review stage.

Changxin's IPO prospectus revealed a wealth of previously unavailable information. Combining SemiAnalysis's Memory Model allows for a more accurate assessment of Changxin's current position and future trajectory.

From a high-level perspective, by almost all measures, Changxin is the world's fourth-largest DRAM manufacturer and is widening its lead over second-tier storage vendors. In full-year 2025, Changxin's revenue increased by 156% year-on-year to approximately $8.6 billion, compared to around $3.3 billion in 2024 and around $1.2 billion in 2023. Net profit also turned positive for the first time, reaching $1 billion. Nevertheless, Changxin's 2025 revenue is still far below Samsung (approximately $72.3 billion), SK hynix (approximately $52.1 billion), and Micron (approximately $37.2 billion)'s DRAM sales.

Figure: Global DRAM Manufacturer Revenue Comparison (Source: SemiAnalysis Memory Model)

In the first quarter of 2026, Changxin reported revenue of $7.3 billion, a nearly 700% year-on-year increase, with quarterly revenue approaching the full-year level of 2025. The operating profit margin also sharply expanded to about 70%.

SemiAnalysis believes this is just the beginning. Based on the IPO filing alone, the company is expected to see a 7x year-over-year revenue growth in the first half of 2026, exceeding $16 billion. For the full year 2026, SemiAnalysis estimates that ChangXin's revenue could surpass $50 billion. If achieved, this would mean the company has more than doubled its revenue annually since 2023, with a year-over-year growth of over 6x in 2026.

The driving force behind this explosive growth, rather than being attributed to technology or market share, is more aligned with the cycle itself. Looking closely at the data: in the first quarter of 2026, ChangXin's bit shipments only grew by 11%, but the ASP (Average Selling Price) rose by around 57%. Previously, in the third and fourth quarters of 2025, the ASP increase was 63% and 68% respectively. What truly boosted the performance was the meteoric price surge rather than a significant grab of market share from peers. Based on bit shipments, SemiAnalysis models show that ChangXin's market share will increase from 9% in 2025 to 12% in 2027. A 3-percentage-point increase in market share may seem small, but in a market that SemiAnalysis predicts will be close to a $1 trillion scale by 2027, this is substantial.

Figure Caption: CXMT's ASP vs. bit shipment trend (Source: SemiAnalysis Memory Model)

Misconceptions of the "Chinese Memory Market Impact" Narrative

For readers who have not closely followed ChangXin or the memory market, a more intriguing finding is the comparison of ChangXin's pricing with industry leaders. Based on data from the Memory Model, ChangXin's DRAM ASP challenges a common misconception: that Chinese memory, structurally cheaper, would disrupt the market and depress global prices. While this may have been true in certain past instances, it is not accurate in this current cycle.

Take the first quarter of 2026, for example, where ChangXin's DRAM ASP was only about 5-10% lower than Samsung, SK Hynix, and Micron. SemiAnalysis expects this trend to continue for the full year 2026, with the gap gradually widening. The widening gap is not due to inherent pricing differences but rather a shift in product mix. Leading manufacturers have a higher proportion of server DRAM and HBM shipments, and the pricing outlook for server DRAM is more favorable than consumer-grade DRAM.

By the end of 2027, SemiAnalysis expects that Server DRAM and HBM will account for over 50% of the DRAM end-market demand. Due to the higher price per GB of Server DRAM and HBM, leading manufacturers will further widen the gap with ChangXin in terms of ASP, especially considering the substantial HBM price increase expected in 2027.

Caption: DRAM Manufacturer ASP Comparison (Source: SemiAnalysis Memory Model)

Profit Margin: A Gift of the Cycle

The strong ASP tailwinds have significantly improved ChangXin's profit margin. The full-year gross margin reached 37.8% in 2025, close to Samsung's 39.4% and Micron's 39.8%, but far below SK Hynix's 60.4% (SK Hynix benefiting from a higher proportion of HBM shipments). ChangXin's approximately 38% gross margin, compared to -113% in 2023 and -4.7% in 2024, represents a huge leap. 2025 not only marked a historical high for ChangXin's gross margin but also the company's first positive gross margin.

Caption: DRAM Manufacturer Gross Margin Comparison (Source: SemiAnalysis Memory Model, Company Reports)

Entering 2026, the profit margin further improved. The first-quarter operating margin reached 70%, with SK Hynix at 73%, Samsung at 81%, and Micron at 84% during the same period. In addition to ASP growth, ChangXin's margin improvement also benefited from its almost exclusive focus on commodity DRAM products—in the current environment, the margin for commodity DRAM is actually higher than HBM. According to the prospectus, around 99% of the company's bit shipments in 2025 were traditional LPDDR and DDR products, with HBM contributing very little to revenue and profit.

Caption: DRAM Manufacturer Operating Margin Comparison (Source: SemiAnalysis Memory Model, Company Reports)

A simple DDR5 unit cost analysis provides a clearer picture. SemiAnalysis found that ChangXin's DDR5 cost per bit is still over 30% higher than the three major players. However, due to the strong pricing of DDR5 in the first quarter of 2026, ChangXin's gross margin has been pushed to over 70%. This means that the improvement in ChangXin's profit margin is mainly being driven by pricing rather than a substantial enhancement in product competitiveness or cost structure.

Caption: DDR5 Cost per Bit Comparison (Source: SemiAnalysis Memory Model)

Capacity Expansion: Closing in on Micron

In addition to record profits, ChangXin is also catching up in terms of capacity. By the end of 2026, SemiAnalysis expects ChangXin to reach approximately 350,000 wafers per month, slightly below Micron's approximately 385,000 wafers per month. In terms of wafer capacity ranking, ChangXin is poised to become the third-largest memory manufacturer in the industry.

Caption: Global DRAM Manufacturers' Monthly Wafer Capacity Comparison (Source: SemiAnalysis Memory Model)

However, ChangXin still lags behind the two giants: Samsung at around 720,000 wafers per month and SK Hynix at around 595,000 wafers per month. By 2027, with the initial ramp-up in Shanghai Phase 1 and full production in Hefei and Beijing, ChangXin's capacity can reach around 420,000 wafers per month, accounting for approximately 17% of global DRAM capacity, up from around 13% in 2025. In terms of bit shipment volume, the market share is projected to increase from 9% in 2025 to 12% in 2027.

By 2028, with full production in Hefei and continued ramp-up in Shanghai Phase 2, SemiAnalysis predicts that ChangXin will reach 500,000 wafers per month, representing approximately 17% of global DRAM supply.

Caption: CXMT Hefei Plant Capacity (Source: SemiAnalysis Memory Model)

Concerns of Oversupply: Nothing to Fear for at Least Two Years

Given ChangXin's increasingly significant role in global DRAM capacity, as in past cycles, investors are worried that Chinese manufacturers could cause a supply-demand imbalance. SemiAnalysis believes that this concern has been exaggerated for at least the next two years. Taking into account incremental capacity from ChangXin and other memory manufacturers, assuming a utilization rate of over 90%, the DRAM supply remains extremely tight.

Caption: DRAM Supply-Demand Balance (Source: SemiAnalysis Memory Model)

Looking solely at ChangXin's capacity expansion pace: adding approximately 85,000, 70,000, and 80,000 wafers per month in 2026, 2027, and 2028, respectively, compared to Samsung's 15,000/50,000/110,000, SK Hynix's 60,000/60,000/90,000, and Micron's 30,000/90,000/115,000. Even with this added capacity, DRAM is expected to face a high single-digit percentage shortage in 2026, with the gap widening to low to mid-teens in 2027. SemiAnalysis has previously elaborated on why DRAM may remain undersupplied until 2028.

ChangXin does not have the ability to irrationally accelerate capacity expansion beyond the current pace to disrupt the market because the construction cycle of wafer fabs is too long. The currently highly favorable pricing environment is indeed a key driver of ChangXin's performance surge—ChangXin certainly hopes this environment will persist. SemiAnalysis has not seen any signs in the tracked wafer fab construction progress that indicate this possibility, but it is worth emphasizing that the total wafer capacity at full production in the Shanghai plant can exceed 400,000 wafers per month.

HBM: ChangXin's Dilemma

Regarding HBM, ChangXin's wafer allocation is extremely limited. By the end of 2025, of ChangXin's approximately 2.65 million wafers per month, only about 5,000 wafers are allocated to HBM. SemiAnalysis expects this number to increase to around 30,000 wafers by the end of 2026 and approximately 55,000 wafers by the end of 2027. This aligns with the IPO disclosure indicating that about 99% of revenue in 2025 came from DDR and LPDDR.

Caption: CXMT HBM Wafer Capacity Allocation (Source: SemiAnalysis Memory Model)

However, this allocation pattern may change. China's drive for AI computing power autonomy may clash with the company's commercial priorities, and this drive is expected to strengthen over time. SemiAnalysis has factored in the government-guided shift of ChangXin towards HBM in its forecast, expecting accelerated HBM capacity expansion in 2027 and 2028. It is projected that ChangXin's HBM capacity will reach 55,000 wafers per month in 2027 and 100,000 wafers per month in 2028, increasing its share of global HBM wafer supply from 1% in 2025 to 12% in 2028.

It is essential to remember that ChangXin is unlike other memory manufacturers; it is not only an economically and technologically critical company but also a strategic asset that the country can leverage to advance its policy objectives.

From a short-term business standpoint, ChangXin's prioritization of capacity allocation to commodity DRAM rather than HBM is reasonable. The current profit margin of commodity DRAM is significantly higher than that of ChangXin's HBM products, and the bit output per unit area is over three times greater for commodity DRAM. At a stage where HBM technology is not yet mature, a substantial investment in HBM capacity would consume scarce wafer capacity that could otherwise be used for commodity DRAM with higher profit margins and larger shipments. However, China must push forward with HBM deployment as sales of HBM to China are severely restricted by U.S. export controls, and Korean manufacturers rely on some loopholes to ship to China.

HBM Technology Gap

In terms of technological readiness, SemiAnalysis believes that ChangXin is still struggling to achieve production stability for HBM3 8-Hi and faces even greater challenges for 12-Hi.

In the upstream process, ChangXin has made progress in the production stability of its G4 (equivalent to 1z node), and most of the DRAM output in 2026 will be based on the G4 process. However, for the DRAM core chips used in HBM, due to the larger die size and stricter performance requirements, the front-end wafer-sort yield for HBM should be significantly lower than that of commodity DRAM. SemiAnalysis believes that the front-end yield remains a major challenge for ChangXin, with a considerable gap compared to peers. Although there has been an improvement in G4 yield, the lower profit margins in 2024 and 2025 suggest that it may still be below the industry standard mature yield level of 85-90% for the 1z node. This implies that equipment constraints and manufacturing experience are still ongoing barriers that ChangXin needs to overcome.

Caption: CXMT DRAM Process Node Roadmap and Yield (Source: SemiAnalysis Memory Model)

The next-generation process node, G5 (equivalent to 1a node), theoretically can continue to advance without relying on EUV lithography machines like Micron's 1a, but will face increasingly significant manufacturing and design challenges. These challenges will be further exacerbated when applying this node to HBM bare die.

Die stacking is the biggest obstacle for CXMT's HBM. HBM stacking typically brings about severe technical challenges: thermal stress, die cracking, warpage, bond defects, and yield losses in multi-layer stacking. As CXMT advances from HBM3 8-hi to HBM3 12-hi and even HBM3E, these issues become more severe, as CXMT's manufacturing experience with 12-hi and higher HBM is still lacking.

The stacking challenge is not unique to CXMT. Leading manufacturers also face issues such as die cracking, thermal management, and yield losses on 12-hi HBM4. 16-hi and even 20-hi are even more challenging—Rubin Ultra is expected to adopt 12-hi HBM4E instead of 16-hi for several reasons, including supply: 16-hi requires more DRAM wafers, is harder to manufacture, results in greater wafer loss, and provides fewer effective bit supplies.

SemiAnalysis believes that CXMT is increasingly likely to skip HBM3 and directly focus on HBM3E 8-hi and 12-hi. There are two reasons for this: first, customers will need more competitive HBM products in the 2027 timeframe, and second, mainstream accelerators will be equipped with HBM3E, HBM4, and HBM4E by then.

Caption: Global HBM Roadmap Comparison (Source: SemiAnalysis Memory Model)

Regarding back-end packaging, while there is still debate over whether CXMT uses MR-MUF or TC-NCF, the packaging challenges are relatively more controllable because the company and its packaging and testing partners face fewer restrictions under export controls. CXMT has always had close cooperation with top OSATs such as TFME, and its back-end capabilities should gradually improve, but there is still a gap compared to leading memory manufacturers.

Based on current manufacturing challenges, SemiAnalysis models the front-end and back-end yields of Longxin's HBM3 8-hi at approximately 35% and 70%, respectively, with an overall yield of only about 25%. For HBM3 12-hi or HBM3E 12-hi, due to higher stacking and bonding difficulties, the overall yield should be even lower. At this yield level, with the same wafer capacity, Longxin's HBM output is far below that of leading manufacturers. More critically, the profit margin of the HBM output is extremely low, especially compared to the current pricing environment of bulk DRAM.

The challenges facing Longxin's HBM are also reflected in its product penetration. SemiAnalysis believes that perhaps only Huawei, Cambricon, and a few emerging Chinese AI chip startups will adopt Longxin's HBM, although the adoption rate may be significant. Domestic AI accelerator manufacturers, if possible, still tend to use foreign HBM3 or even HBM3E, whether through any available channels or from inventory before the export control deadline in December 2024. With the rapid growth of capital expenditure and AI infrastructure construction by Chinese domestic cloud providers, the demand for domestic HBM is also growing rapidly.

One notable exception: Huawei and Longxin will develop custom HBMs that are not based on JEDEC standards and PHY, which will help mitigate the bandwidth disadvantage.

The HBM supply constraints faced by China may be more severe than implied by the slow development of domestic HBM itself. The supply from the three major HBM suppliers is already tight, and due to the export control deadline in December 2024, they have been restricted from selling HBM2E and more advanced HBM products to China. In a tight supply environment, these manufacturers are even less willing to risk violating regulations by selling to China.

However, the transshipment and smuggling of HBM make the situation even more complex. Some Chinese companies are still obtaining HBM3 through various channels. Transshipment through overseas offices or third-country partners remains a method; some OSATs or intermediaries in third countries are also facilitating this distribution. Entities are exporting in the form of partially assembled systems or modules (not considered finished GPUs or ASICs, therefore still allowed to be exported to China), and the HBM is subsequently dismantled and repackaged onto domestic GPUs or ASICs.

What the IPO Structure Reveals

Longxin could become one of China's largest semiconductor IPOs, with its ownership structure being more noteworthy than its financial statements. Longxin reports a consolidated net profit of ¥7.14 billion in 2025, but the net profit attributable to the parent company's shareholders is only ¥1.87 billion, with 74% attributable to minority interests.

The reason lies in the equity structure. ChangXin only holds 30.68% economic interest in ChangXin New Bridge and 31.72% economic interest in ChangXin Collecting Electricity Beijing, but through a long-term concerted action arrangement, it controls 73.01% and 75.32% of the voting rights, respectively. This allowed the company to consolidate most of the wafer fab it actually does not own, thereby overestimating the combined data by about four times in terms of the actual profit available to public shareholders.

Caption: CXMT Merged Profit vs. Parent Profit (Source: SemiAnalysis Memory Model, Company Reports)

The same voting structure also renders the company's declaration of "no controlling shareholder, no ultimate controller" unconvincing (the prospectus lists it as a formal governance risk). ChangXin, through a concerted action agreement, exercises majority voting control over the wafer fab, with the National Integrated Circuit Industry Investment Fund Phase II, entities of Hefei and Anhui collectively holding stakes well over 30% post-listing. This arrangement appears to be aimed at managing export controls and the perception of foreign investors, at a time when ChangXin's relationship with the Chinese government is under the most scrutiny.

Caption: CXMT Ownership Structure Chart (Source: SemiAnalysis Memory Model, Company Reports)

Valuation: The Undervalued Bottom Price

ChangXin plans to raise 29.5 billion RMB (about $4.1 billion) by issuing 10-15% of the post-listing total share capital. Fully financing through an IPO means: at 10% dilution, approximately 4.41 RMB per share, and at 15% dilution, around 2.78 RMB (the June 2025 financing price was 2.63 RMB). The low-end price has almost no premium compared to the previous round, despite achieving $7.3 billion in revenue and $4.8 billion in net profit in the first quarter of 2026. The 2.78 RMB corresponds to a valuation of about 197 billion RMB (about $27 billion), equivalent to only 1.8 times the annualized net profit in the first half of 2026. SemiAnalysis believes that this bottom price valuation is too low, and the actual pricing should be much higher.

Caption: CXMT IPO Valuation Analysis (Source: SemiAnalysis Memory Model, Company Reports)

Fundraising Purpose: Focus on Bulk DRAM, No Mention of HBM

The ¥29.5 billion fundraising purpose solidifies ChangXin's current priorities. Of this amount, ¥20.5 billion (69.5%) is allocated to wafer fabrication lines and DRAM technology upgrades, while ¥9 billion (30.5%) is designated for forward-looking DRAM research. The prospectus did not disclose any specific HBM projects, nor was HBM mentioned at all. The project description focuses on an updated technological platform, product iterations, and the migration of existing production lines to mid-to-high-end DRAM. The core purpose of the IPO is to strengthen ChangXin's DRAM manufacturing and technological foundation, without any public financial commitment to recent HBM expansions.

Caption: CXMT IPO Fundraising Allocation (Source: SemiAnalysis Memory Model, Company Reports)

Timing Cycle Warning

The magnitude of profit fluctuations necessitates a reminder about the timing cycle. In its December 2025 prospectus, ChangXin anticipated a full-year net loss of ¥600 million to ¥1.6 billion in 2025. Five months later, an updated prospectus reported a profit of ¥1.87 billion, with consolidated profits exceeding more than twice the previous high-end estimate. This also illustrates how quickly DRAM peak pricing can change the valuation denominator—both ways.

Alibaba's Dual Role

One final detail: Alibaba's evolving role in ChangXin's shareholder list has shifted the interpretation of ChangXin's demand side. Alibaba Cloud is both a core hyperscale customer and a shareholder and endorser with close to a 4% stake, standing alongside Zhu Yiming's Zilliq Innovations (holding approximately 1.8%). Domestic demand levels have been somewhat secured, providing an advantage that Korean giants do not possess in their home market. While the percentage may be small, the significance is much greater.

Disclaimer: The latter part of this article, which delves into SemiAnalysis' paid content on CXMT's equipment ecosystem, export control impact, and China's storage and computing ambitions, is not included in this compilation.

Original Article Link