Huawei Ascend 950PR matrix computing is only 40% the speed of H100, and DeepSeek is squeezing performance out of software.

Beating AI News Flash: Last year, DeepSeek attempted to train R2 using Huawei Ascend chips, but even with Huawei engineers on-site assisting, they could not get it to run. There were issues with chip stability, cross-card communication, and software support. This year, the two sides continue to deepen cooperation. At the end of September, DeepSeek集中公开了六套昇腾适配代码; in October, it was reported that Huawei is adjusting the design of its next-generation chips according to DeepSeek's model requirements.

Semiconductor research firm SemiAnalysis recently published actual test results for the Ascend 950PR. The researchers selected 1,055 sets of matrix calculations commonly used in large models and found that Huawei's own low-level programs already enable the 950PR to achieve 86% of its own attainable computing power, higher than NVIDIA H100's 75.5%. However, the actual computing speed is still only 43% of H100's, and compared with the newer B300, it is only 21%. These results have not yet used DeepSeek's newly ported operators.

DeepSeek is reducing data movement and waiting time from the software side. For example, when running attention computation, the two pieces of data that originally needed to be read separately can be fetched all at once after FlashMLA adjusts the storage method. Another tool, TileLang, allows the chip to preload the next batch of data while computing. SemiAnalysis's actual tests showed that automatic scheduling reduced the time required for some small computing tasks by up to about 40%. DeepSeek has also ported DeepEP, which handles MoE expert communication, but communication and computation still compete for memory bandwidth, and Huawei plans to continue improving the firmware.

The 950PR tested this time is mainly aimed at inference input processing, while the 950DT, which DeepSeek plans to use for large-scale pretraining as early as the end of the year, is a different chip. The two sides have previously carried out thousand-card-level tests, but to enable tens of thousands of chips to continuously complete a round of large-model training, more complex coordination and stability issues still need to be solved.