Samsung Explores New Memory Technology: Vertical Stack Above AI Accelerator, Density Exceeds Traditional HBM5 Tenfold

August 5th, Samsung Electronics unveiled its V10 Bonding V-NAND prototype product at the Future Storage and Memory Conference (FMS) held in Santa Clara, California, USA.

The chip features a structure of over 400 layers and adopts a new wafer bonding architecture to increase storage density and enhance performance. Samsung stated that its BV-NAND technology has increased the storage density by approximately 58% compared to the previous generation V9 NAND, while also improving read, write, and I/O performance to meet the growing demand of AI systems for higher capacity, more energy-efficient storage solutions.

Samsung also showcased its self-proclaimed industry-first zHBM and zNAND-O architecture concept models. This technology stacks storage units vertically to store more data in a smaller space. Unlike the traditional HBM alongside AI processor packaging, Samsung's zHBM vertically stacks the storage on top of the AI accelerator to shorten data transfer distances, increase bandwidth, and improve energy efficiency. Samsung stated that its wafer bonding technology is expected to achieve over 10 times the storage density of traditional HBM5 memory, increase energy efficiency by 3 times, and reduce thermal resistance by more than half.