Morgan Stanley Insights: AI Chip Frenzy, Can Power Keep Up? Implied Demand of Around 38GW by 2027

TL;DR
· Morgan Stanley's latest Asian supply chain check converts AI expansion into a more intuitive power number: based on an estimated total of around 19 million CoWoS implied GPUs and ASICs by 2027, with an average 2kW TDP per chip, the power capacity associated with these chips is approximately 38GW.
· Of this, NVIDIA accounts for about 16GW, Google around 9GW, AMD around 7GW, AWS around 2GW, while Microsoft, Meta, and other manufacturers each account for around 1GW.
· It is important to note that the 38GW is not the total power consumption of global AI data centers at that time, nor is it the confirmed power capacity. It does not fully account for the power consumption of CPUs, networks, storage, cooling, and other supporting facilities, but rather represents a stress test derived from the volume of chip shipments: can the power infrastructure handle these chips if AI accelerators ramp up production according to the supply chain model in 2027?

This means that the constraint of AI computing expansion is shifting from "Can GPUs be produced" to further extending to whether HBM, CoWoS, testing, rack delivery, and power access can all be in place simultaneously.

38GW Stress Test, Pushing AI Bottleneck to Power

Morgan Stanley's calculation this time is based on two core assumptions: the quantity of GPU and ASIC chips corresponding to CoWoS in 2027 is approximately 19 million chips, and the average TDP per chip is calculated at 2kW, resulting in a total power demand of around 38GW.

The 2kW is an average assumption adopted for estimating the total, and does not mean that all GPUs and ASICs have the same power consumption. The 38GW also does not equate to the actual operating load of data centers, as chips will not constantly run at full load, and CPUs, networks, storage, and cooling systems in servers will consume additional power.

However, this number is still useful as a reference point. Over the past two years, the AI ​​supply chain discussion has mainly focused on GPU allocation, HBM supply, and CoWoS capacity. As chip shipments continue to rise, factors such as grid connection, substation construction, data center location selection, and long-term power purchase agreements may directly affect whether the chips can be transformed into actual usable computing power.

Chip delivery is just the first step. After GPUs or ASICs enter the data center, they still need supporting servers, racks, networks, cooling, power, and operations and maintenance systems. If infrastructure development lags behind chip shipments, the market may see a "chips are here, but the data center and power are not ready" mismatch.

By 2027, GPU/ASIC chip implied power demand is about 38GW, with NVIDIA at 16GW, Google at 9GW, and AMD at 7GW.

For NVIDIA, the 16GW implied demand also explains why the company continues to increase the GPU density per rack. The report states that NVIDIA hopes to connect more GPUs through a scale-up architecture in the long term to increase rack-level computing power and performance.

However, the first-generation Kyber solution of the Rubin Ultra rack still faces PCB and cooling challenges and may continue to use the Oberon NVL72 design, then scale up to the NVL576 size through CPO or NPO interconnection. Increasing rack density will not eliminate power demand but will instead concentrate power supply, cooling, and interconnection pressure on higher-spec data center designs.

HBM and CoWoS Synchronized Expansion, Rubin Ultra Specifications Still Pending

Outside of power, HBM and advanced packaging remain the main constraints for AI chip expansion around 2027.

According to the Morgan Stanley supply chain model, the HBM demand corresponding to AI chips in 2027 is about 486.18 billion Gb. The number of CoWoS configurations listed in Exhibit 3 is approximately 2.664 million wafers, while the global CoWoS demand given in Exhibit 5 is about 2.694 million wafers, with a slight difference due to different statistical scopes.

The report also estimates that by 2027, the wafer revenue market size for AI computing chips will reach at least $58.8 billion. NVIDIA remains the largest demander of CoWoS, with an estimated allocation of about 1.222 million wafers; AMD and Broadcom are around 530,000 wafers and 484,000 wafers respectively.

By 2027, the AI HBM demand is expected to reach around 486 billion Gb, including the CoWoS configurations with HBM for various GPUs and ASICs.

One key variable that still remains in demand forecasting is the finalization of the HBM configuration for Rubin Ultra.

Supply chain checks indicate that Rubin Ultra may adopt a tiered specification, with the high-end version using HBM4e 8Hi, while the low-end version may opt for either HBM4 12Hi or 8Hi. Morgan Stanley anticipates that NVIDIA might make a final decision by the end of Q3 2026.

This adjustment primarily reflects three key pressures: HBM production capacity constraints, rising memory costs, and varying AI workloads with different requirements for capacity and bandwidth. The report suggests that reducing the impact of HBM configuration on inference workloads may be more significant than prefill, especially in large-context mega models.

It is important to note that Exhibit 3 still assumes a calculation based on Rubin Ultra configured with HBM4e 12Hi, with a total capacity of 384GB per chip. Therefore, the demand for 486 billion Gb of HBM has not yet fully accounted for potential tiered down-spec scenarios. If the final configuration is reduced, the HBM usage per chip may decrease, but the lower memory cost could also drive chip shipments up, partially offsetting the impact of the decrease in usage per chip.

Micron's public information indicates that its HBM4 has entered mass production, with HBM4E expected to start production in 2027. The supply side is advancing new products, but the ultimate configuration choice for Rubin Ultra still depends on NVIDIA's overall trade-off between performance, cost, and supply assurance.

The shipping pace of the Rubin series remains aggressive. The report estimates that total shipments of Rubin and Rubin Ultra will reach close to 7 million units in 2027, with approximately 5.92 million units for Rubin and around 1.04 million units for Rubin Ultra; shipments of Rubin NVL72 racks could potentially reach about 90,000.

Rubin is expected to ramp up from Q3 2026, with rack shipments commencing in Q4. The report also suggests that previous market concerns about Blackwell "inventory" are more related to supply chain buffer inventory, which is expected to be completely absorbed by 2026.

Rubin and Rubin Ultra Chip Shipments and Rubin NVL72 Rack Shipment Forecast.

This means that from the second half of 2026 to 2027, NVIDIA's supply chain needs to simultaneously complete Blackwell inventory digestion, Rubin ramp-up, HBM specification transition, and rack delivery. Any slowdown in any link may affect the final deliverable computing power scale.

Google TPU Increases to 7.35 Million Units, Orders Transferred to Test Chain

In addition to NVIDIA, Google TPU is another significant growth theme in the report.

According to Morgan Stanley's forecast, Google TPU shipments will increase from 3.7 million units in 2026 to 7.35 million units in 2027. Among them, v8i involving Broadcom is expected to ship 4 million units, v8t involving MediaTek is expected to ship 3 million units, v9 is expected to ship approximately 150,000 units, and the remaining around 200,000 units are from v7.

Google's various generations of TPU shipment forecasts and their potential contribution to KYEC's revenue.

TPU volume production will transfer orders to chip design, wafer manufacturing, advanced packaging, and testing. The report estimates that TPU-related business may account for 7% to 8% of KYEC's revenue in 2026 and slightly over 10% in 2027, including final testing and some wafer probing income.

If Google's CPU, TPU, final testing, and some wafer probing businesses are all included, Google-related demand is expected to account for 10% to 15% of KYEC's revenue in 2027, higher than 8% to 10% in 2026.

Testing demands are also becoming more complex. The report states that the 3nm TPU involving MediaTek is expected to undergo Burn-in testing to improve AI chip performance stability and reliability; Google's CPU project also requires Burn-in and system-level testing.

More complex testing processes and longer test cycles will increase testing factory orders, but whether testing capacity will become a bottleneck also depends on the joint changes in single-chip test time and overall shipment volume. The report also suggests that shortening some test times may alleviate recent capacity pressures, so it is not a simple equation to equate the growth in testing demand with inevitable capacity shortages.

38GW is Not the End Demand, But a Delivery Capacity Test

The most notable aspect of this supply chain check is not just providing more AI chip shipment figures, but placing the main expansion constraints for 2027 in the same model: NVIDIA continues to increase GPU density, Google's TPU ramps up quickly, HBM and CoWoS demand rise in sync, and chip implicit power demand is pushed up to 38GW.

These figures still rely on several assumptions. Rubin Ultra's layered HBM approach has not been finalized yet, the impact of reducing memory configuration on long context decoding performance still needs to be validated; CoWoS and HBM capacity need to expand as planned; server, rack, power, and cooling infrastructure also need to keep pace with chip delivery.

Interconnect solutions may also bring differences. The report states that due to domestic foundry process limitations, the SerDes speed of Chinese AI GPU manufacturers may still remain at 100Gb/s per channel, so their super node architecture is increasingly adopting NPO interconnects, while NVIDIA has long been more focused on CPO. Different paths will impact super node design, deployment costs, and system efficiency.

Therefore, 38GW is not an exact prediction of the actual power consumption in 2027, but a stress test derived from the chip shipment side. It shows that the demand for AI chips is still strong, and it also reminds the market: the decision on whether AI computing power can be realized may no longer be just about GPU production scheduling, but about whether HBM, CoWoS, testing, racks, and power can all come together at the same time.